1. Technical Field
Methods for manufacturing semiconductor devices which include partial implantation techniques are disclosed.
2. Description of the Related Art
Generally, methods for manufacturing semiconductor memory devices, such as dynamic random access memory (DRAM), consist of several unit processes. The unit processes include deposition, etching, and implantation processes, etc., and are conventionally performed on a wafer-by-wafer basis. However, uniform process results are difficult to achieve. For example, uniform thicknesses of the stacked layers and etching ratios and uniform density of ions as throughout the area of the wafer are difficult to obtain because it is impossible to accurately control the large number of variables associated with the unit processes. Therefore, it can be said that process errors due to unpredictable or inaccurately controlled process variables are an inherent aspect of semiconductor device manufacturing.
As expected, process errors ultimately deteriorate the characteristics of semiconductor devices to be manufactured. As an example, transistors often fail to maintain a uniform threshold voltage throughout the wafer. Even if the threshold voltage is adjusted to be uniform throughout the wafer via the implementation of an ion implantation process prior to forming a gate stack, the threshold voltage can become non-uniform during subsequent processes, resulting in uneven distribution of the threshold voltage throughout the wafer.
In a subsequent formation of a gate insulation layer, an oxide layer as the gate insulation layer is formed in a non-uniform thickness throughout the wafer. This makes it impossible to achieve a uniform threshold voltage distribution throughout the wafer even if the ion implantation process is performed to impart the wafer with a uniform threshold voltage.
Further, when source/drain regions having lightly doped drain (LDD) structures are formed, low-density ions are first implanted after formation of the gate stack, forming source/drain extension regions. Subsequently, a gate spacer is formed at the side wall of the gate stack, and then, high-density ions are implanted to form deep source/drain regions. However, there are problems in that the oxide layer and nitride layer of the gate spacer are stacked at a non-uniform thickness throughout the wafer, and that it is impossible to achieve a uniform etching ratio even when using an etch-back process. Thus, the gate spacer exhibits an uneven thickness on the wafer. When the gate spacer is used as an ion implantation mask to form the deep source/drain regions, furthermore, it inevitably adversely affects the threshold voltage in parts of the wafer.
To solve the uneven distribution problem of the threshold voltage caused by non-uniform process results described above, a partial implantation method has been proposed. The partial implantation method is a method of implanting ions, that act as impurities, namely, dopant providing a threshold voltage adjustment, into respective regions of a wafer at varying densities in consideration of variations in the threshold voltage in subsequent processes.
FIG. 1 is a diagram illustrating a conventional partial implantation method. A wafer 100 is divided into a plurality of regions according to the density of dopant ions to be implanted thereto. More specifically, based on a boundary line 110 crossing the center thereof, the wafer 100 is divided into an upper region 120 at the upper side of the boundary line 110 and a lower region 130 at the lower side of the boundary line 110. Here, it should be understood that the terms “upper” and “lower” are used for easy explanation of the wafer structure with reference to FIG. 1, and are not intended to limit the positional relationship therebetween.
It will be understood that the wafer may be divided into three or more regions as occasion demands. Ions having different densities, in consideration of the threshold voltage variation in subsequent processes, are implanted to the respective divided regions, namely, the upper and lower regions 120 and 130. For example, when it is expected that the threshold voltage of the upper region 120 will be lowered during subsequent processes, dopant ions are implanted at a relatively lower density than the normal density of ions that are implanted in a general implantation process by approximately 5%, thereby increasing the threshold voltage of the upper region 120. Conversely, when it is expected that the threshold voltage of the lower region 130 will be increased during subsequent processes, dopant ions are implanted at a relatively higher density than the normal density by approximately 5%, thereby lowering the threshold voltage of the lower region 130. This enables both the upper and lower regions 120 and 130 of the wafer 100 to achieve a uniform threshold voltage distribution in spite of such a threshold voltage variation in subsequent processes.
FIG. 2 is a graph illustrating the density distribution of dopant ions implanted by the conventional partial implantation method. The abscissa of the graph represents the length of the wafer 100 measured along the line II-II′ that intersects the boundary line 110 of the wafer 100. The origin of the abscissa indicates one point on the perimeter of the circular wafer 100, and the right end of the abscissa indicates the opposite point on the perimeter of the wafer 100 that is shown as a flat zone in FIG. 1. Further, a dashed line 110a indicates the boundary line 110 of FIG. 1. A region at the left side of the dashed line 110a indicates the upper region 120 of the wafer 100, and a region at the right side of the dashed line 110a indicates the lower region 130 of the wafer 100. The ordinate of the graph represents a therma-wave (TW) signal, which is proportional to the density of the dopant ions implanted in a wafer. Thus, the density distribution of the dopant ions implanted in the wafer 100 can be recognized by measuring the therma-wave signal. From the description as stated above with reference to FIG. 1, it can be clearly understood that the density of the dopant ions implanted in the upper region 120 of the wafer 100 is relatively low and the density of the dopant ions implanted in the lower region 130 of the wafer 100 is relatively high.
Although the conventional partial implantation method as stated above can eliminate the non-uniformity of the threshold voltage throughout the respective regions of the wafer to some extent, it has a limitation when adjusting the density of dopant ions at a boundary line between the respective regions. That is, it is difficult to adjust the density of dopant ions in the vicinity of the boundary line 110 of the wafer 100 shown in FIG. 1. As is clearly illustrated in the graph of FIG. 2, the density of the dopant ions is not constant in the vicinity of the boundary line 110, but increases gradually from the upper region 120 to the lower region 130. The slope of the density is represented as a dotted line 200 in the vicinity of the dashed line 110a of the graph of FIG. 2 corresponding to the boundary line 110 of the wafer 100. The dotted line 200 is determined based solely upon the density of dopant ions implanted in the wafer 100, and cannot be freely adjusted. As will be easily understood, the slope of the dotted line 200 should be high in the vicinity of the boundary line 110 in order to achieve a wide difference between the characteristics of transistors in the respective regions divided by the boundary line 110. Conversely, when it is desired to narrow the differences between the characteristics of the transistors, the slope of the dotted line 200 should be low in the vicinity of the boundary line 110. However, the conventional partial implantation method cannot provide free adjustment of the slope of the dotted line 200, namely, the density of the dopant ions.